1. Field of the Invention
The present invention relates to a method of forming a pre-metal dielectric (PMD) layer and, more particularly, to forming a PMD layer using an undoped silica glass (USG), ion implantation, and annealing so as to enhance a gap-fill capability, a gettering capability, and electrical properties of a transistor.
2. Description of the Related Art
According to Moore's Law, the degree of integration on semiconductor devices doubles almost every two years. Chip size and design rules shrink accordingly, and new and unexpected problems to be solved are continuously introduced as a result.
The PMD layer is an insulating layer that is provided for separation between a polysilicon gate and an overlying metal layer. The PMD layer should have a good gap-fill capability, a good gettering capability, an easy reflow planarization, and a low moisture absorption.
The gap-fill capability is the ability to fill gaps between adjacent patterns of the semiconductor device. Further, the gettering capability is the ability to trap mobile ions, such as sodium or other metal ions that may degrade device properties.
Silicon oxide (e.g., SiO2) is used often for insulating layers in the semiconductor industry. A silicon oxide PMD layer, however, may have a poor gap-fill capability when used to fill gaps produced by stepped surfaces of the polysilicon gates. Therefore, the silicon oxide PMD layer frequently creates unfavorable voids, by which the PMD layer is not densified and the device is degraded in quality and reliability. Moreover, the voids in the PMD layer may be filled with conductive material in subsequent deposition of conductive material for contacts. The conductive material in the voids may sometimes cause unexpected short circuits between the contacts. This is a serious cause of a drop in yield.
As an alternative to the silicon oxide PMD layer, BPSG (borophosphosilicate glass) or PSG (phosphosilicate glass) may be used for the PMD layer. The BPSG PMD layer may be formed by introducing boron and phosphorus sources into a processing chamber along with the silicon and oxygen sources that normally form a silicon oxide layer. Generally, boron doping enhances a gap-fill capability, and phosphorus increases a gettering capability.
Typically, the BPSG layer may be formed using CVD (chemical vapor deposition) techniques, for example, PECVD (plasma enhanced CVD), APCVD (atmospheric pressure CVD), SACVD (sub-atmospheric pressure CVD), and LPCVD (low pressure CVD). At design rule of about 0.5 μm, a SiH4 BPSG layer is deposited and then reflowed at a temperature of about 900° C. At design rule less than 0.5 μm, an O3 TEOS BPSG layer is deposited using APCVD or SACVD and then reflowed at a temperature ranging from 850° C. to 900° C.
However, at further smaller design rule, for example, less than 0.25 μm, a higher reflow temperature may deteriorate device characteristics. In addition, boron should be added at a specific concentration so as to adequately reflow the BPSG layer. However, above certain boron concentrations, the BPSG layer may often crystallize due to increased moisture absorption. Crystallization may cause or increase the incidence of cracks in the BPSG layer.
The BPSG PMD layer may be replaced by a PSG PMD layer that is formed using PECVD or APCVD. The PSG layer may have a good insulating property and a relatively low reflow temperature. The PSG layer, however, may not only have a high moisture absorption, but also have a high hydrogen and carbon content in the layer. Additionally, PECVD or APCVD process may often produce seams in the PSG layer. Such seams may be easily attacked by slurry during CMP (chemical mechanical polishing) process.
FIGS. 1A to 1C sequentially show a conventional method of forming the BPSG PMD layer.
As shown in FIG. 1A, a gate electrode 11 is formed on a semiconductor substrate 10, and then a nitride layer 12 is formed thereon.
Next, as shown in FIG. 1B, a BPSG layer 14 is deposited using a CVD technique, for example, PECVD, APCVD or SACVD at a temperature of 380° C. to 400° C. Unfavorable voids 13 that may be created in the BPSG layer 14 not only disturb densification of the BPSG layer 14, but may also receive conductive material causing defective devices.
Next, as shown in FIG. 1C, the BPSG layer 14 is reflowed through a heat treatment process. The heat treatment process is carried out in order to densify the BPSG layer 14 by removing the voids 13. For example, a rapid thermal process may be carried out for 20 seconds to 60 seconds at a temperature of 700° C. to 1100° C., or annealing may be performed in a furnace for 20 minutes to 60 minutes at a temperature of 700° C. to 1100° C.
The above-discussed conventional method of fabricating the PMD layer is favorable when used to fill gaps with aspect ratios less than about 5:1. However, since the aspect ratio increases with decreasing chip size, the gap-fill process becomes more difficult. So, the voids 13 in the BPSG layer 14 are not always completely removed after reflow with heat treatment.
In order to solve such problems, Korean Patent Registration No. 10-388205 discloses a method that includes forming a barrier on a silicon substrate having a gate, implanting fluorine ions into the barrier, diffusing the fluorine ions through a first heat treatment process, depositing a BPSG layer on the fluorine-diffused barrier, and reflowing the BPSG layer through a second heat treatment process. This method, however, may have limitations on improvements in gap-fill capability.
On the other hand, U.S. Pat. No. 6,013,584 discloses a method using a high density plasma (HDP) CVD technique when forming a PSG layer. This method includes introducing a process gas, such as SiH4, PH3, O2, and argon, into a processing chamber, maintaining a temperature and a pressure of 400˜650° C. and 1˜10 mTorr, respectively, and applying high density plasma bias to a substrate. However, this method may have undesirable effects on electrical characteristics of a transistor due to damage that may be induced by the strong plasma.